Phase lock loops (PLL) are well-known circuits that are used to lock a locally generated signal such as a clock signal to an external or reference signal. This might be applied for example in telecommunications receiver equipment or digital audio equipment which receives a reference signal and needs to generate a local clock signal whose frequency and phase are related to the received reference signal (a condition known as lock) in order to properly receive incoming information signals. A schematic of a PLL is shown in FIG. 1 and comprises a phase and frequency detector (PFD), a charge pump (CP), a loop filter (LF) and an oscillator (VCO) in a feedback loop. The detector (PFD) detects the frequency or phase difference between the signal output by the oscillator (VCO) (the derived clock) and a reference signal (the reference clock). The detector outputs an error signal which is proportional to the frequency and phase difference between the two input signals, which in turn controls the frequency output of the oscillator. This feedback loop allows the generated signal to converge in frequency towards the reference signal. In some implementations either the generated clock from the VCO, or the system reference clock, or both, may be divided in frequency to provide a generated clock at a fixed ratio of frequency to the system reference clock.
The Phase and Frequency Detector (PFD) is also a well-known circuit, an example of which is shown in FIG. 2a. The PFD generates two outputs (UP and DOWN) which are used to control the charge pump or similar controller driving the loop filter which in turn controls the error voltage to the VCO input in order to control the VCO output frequency. A simple PFD typically comprises two flip flop circuits L1 and L2 and a NAND gate N. Taking the rising clock edge from the reference signal rising first, flip flop L1 will latch first so that a reference voltage, usually one of the supply rails Vcc, will be output at Q, and hence at the UP output. This is followed by the corresponding clock edge from the oscillator signal or derived clock, which latches flip flop L2 to provide Vcc at its output Q (the DOWN signal). This together with the Vcc output Q of L1 triggers the NAND gate N to reset both flip flops L1 and L2, such that their outputs Q remain at ground or 0V until the next rising clock edge at their inputs. The UP and DOWN signal waveforms can be seen in FIG. 2b. The duration of the DOWN output is small and related to the propagation time through the NAND gate N and the reset circuitry of the flip-flops L1 and L2. The duration of the UP output however is related to the time difference between the rising edge of the Reference signal and the Derived signal. The larger this time difference, the larger the duration of the UP output pulse. Similarly, if the Derived signal leads the Reference signal, output pulses will appear on the DOWN output which are proportional to the amount of the lead. The UP and DOWN outputs feed a controller such as a charge pump which generates an increase or decrease in the loop filter output voltage depending on which signal leads, and this in turn either slightly increases or decreases the VCO's output frequency as appropriate.
As long as the phase difference between the reference and derived clocks remains less than 2π, the output pulse duration is proportional to the phase difference, and the PFD is said to be in phase acquisition mode. When the reference and derived clocks differ by more than 2π phase difference the operation of the PFD is qualitatively different. FIG. 3a illustrates what happens when the phase difference between the two signals accumulates to exceed 2π. In the case illustrated, the derived clock (DER) waveform is slightly lower in frequency than the reference clock (REF) waveform. Initially (pulse 0), DER leads REF, and the duration of the UP signal (pulse 1), is defined by the propagation delay through NAND gate N and flip-flop L1. At pulse 1, the phase difference is small, so the duration of the UP pulse is also small. As the phase difference increases, the UP signal extends (pulse 2, pulse 3) until it extends over almost the full cycle (pulse 4), as the rising edge of DER occurs only just in time to reset the UP pulse. By the next cycle (pulse 5), no rising edge of DER has occurred by the second rising edge of REF, so UP stays high, and is only reset when DER rises, which happens shortly after this second rising edge of REF. UP then stays low for most of a REF cycle, until the next rising edge of REF generates pulse 6. This pulse is still quite narrow, similar to pulse 2. For this example, with a fixed frequency difference, the chain of events will repeat. So, although the phase difference between DER and REF increases monotonically, the duty cycle of the UP pulses follows a saw-tooth pattern, with discontinuities approximately every 2π.
A similar characteristic for the DOWN pulses will occur if REF progressively lags DER. This can be graphically illustrated by the PFD transfer characteristic of the PFD shown in FIG. 3b. The PFD characteristic clearly shows a series of discontinuities at multiples of 2π, as the output duty cycle repeatedly ramps up to a maximum and then abruptly drops down to zero.
In the context of a PFD operating in a complete PLL, as DER slips relative to REF (or vice versa), this will be seen as the width of UP or DOWN pulses suddenly decreasing during the lock process, as can be seen in FIG. 3a. These discontinuities in the stimulus applied to the subsequent loop filter will cause discontinuities in the slope of the loop filter output voltage, i.e. in the VCO control voltage. Typically the dynamics of the loop filter will show changes in slope polarity at the time when these cycle slips occur, as illustrated in the simulated behaviour shown in FIG. 3c which shows the VCO control voltage when cycle slips are occurring—the troughs in the waveform are symptomatic of cycle slips. When cycle slips are occurring, the dynamic behaviour of the PLL is non-linear, and the behaviour can deviate away from that dictated by linear control theory, generally resulting in increased lock times.
By detecting cycle slips, the VCO control voltage can be adjusted or “corrected” to avoid or minimise these discontinuities and thus improve the lock time of the PLL. Various cycle slip detectors and control voltage correction circuits also known as cycle-slip compensation circuits are described in U.S. Pat. Nos. 6,265,902, 6,466,058, 6,256,362 and US2002/0126787.
In U.S. Pat. No. 6,265,902 the PFD is coupled to two cycle slip detector and correction circuits each comprising an edge triggered counter together with logic circuitry which adds to the UP or DOWN output signals when a respective cycle slip is detected. This is achieved by detecting if the UP (or DOWN) signal is still asserted when a next reference (or derived) signal edge is received. The counter outputs a correction signal, which is combined (OR'ed) with the respective UP or DOWN output. The duration of the correction signal is determined by a load value, which the counter receives as an input.
In U.S. Pat. No. 6,256,362, a more complex PFD is utilised together with cycle slip detectors comprising latches and logic circuitry which combined with a cycle slip counter circuit provide “corrected” UP2 and DOWN2 output signals.
In US2002/0126787, the PFD includes a delay element 36 in its reset circuitry in order to provide for a minimum UP or DOWN output pulse to aid linear operation of the PFD and subsequent charge pump. Lock detection, i.e. generation of a logic signal to flag that the loop and its output frequency have stabilized, is useful since the PLL must be in a stable mode of operation before the derived or generated clock can be reliably used by the rest of the system. Additionally the PLL lock time can be reduced by having a fast lock mode (i.e. wide loop bandwidth), which is used when the PLL is locking, and a slow mode (i.e. tight loop bandwidth), which is used when the PLL is locked.
Some lock detectors detect cycle slip in conjunctions with a complex state machine to determine the lock condition rather than the linear/non-linear modes of operation of the PFD. However a complex state machine can significantly increase cost. An example of this implementation is disclosed in U.S. Pat. No. 6,256,362. Similarly, U.S. Pat. No. 6,466,058 uses a cycle slip detector in tandem with an input signal presence detector.
Other types of lock detector utilise the phase alignment of the UP and DOWN signals, as disclosed in U.S. Pat. No. 6,404,240. However, the relative phasing of the UP and DOWN signals when the system is locked can depend on the operating conditions of the analog circuitry. For example, offsets in the PLL circuitry can give rise to a significant phase offset at the PLL inputs, even though the loop is adequately frequency-locked.